IC manufacturers are employing finer circuit widths, low dielectric constant (low-k) materials, and other technologies to make small, high-speed semiconductor devices. Along with these advancements, the challenges of maintaining yield and throughput have also increased. With regard to reliability, the presence of low-k material near die corners increases the chances of cracks forming, especially in the sawing process.
A semiconductor wafer typically comprises substantially isolated dies (or chips) separated from each other by scribe lines. Individual dies within the wafer contain circuitry, and the dies are separated by sawing and are individually packaged. Alternately, the individual dies may be packaged in multi-chip modules. In a semiconductor fabrication process, the semiconductor device (e.g., an integrated circuit IC) must be continuously tested at every step so as to maintain and assure device quality. Usually, a testing circuit is simultaneously fabricated on the wafer along with the actual devices. A typical testing method provides a plurality of test pads, which are electrically coupled to an external terminal through probe needles, located on the scribe lines. The test pads are selected to test different properties of the wafer, such as threshold voltage, saturation current, gate oxide thickness, or leakage current. Test pads are formed along the scribe lines, thus a logical concept “test line” is used to refer to a strip-like region having test pads therein.
In general, the scribe lines are defined in areas of the multi-layer structure that are without a die pattern and that have a width of about 80 to 100 μm depending on the dimensions of the dies manufactured in the wafer. In order to prevent cracks induced during wafer sawing from propagating into the die, each die is usually surrounded by a seal ring of 3 to 10 μm in width. Nevertheless, during wafer manufacture, damage is often introduced because of the scribe lines. Further, when at least one layer of the multi-layer structure is composed of a metal material with a high thermal expansion coefficient, the dimensional variation of the layer is sufficient to introduce high-level internal stress into the wafer in the area of the scribe line. Consequently, portions of the wafer around the scribe line suffer damage, such as peeling, delamination, or dielectric fracture. The types of scribe line damage mentioned above are usually observed when the multi-layer structure includes an inter-metal-dielectric layer of low dielectric constant (low-k).
When considering a design rule for the placement of test pads on the scribe line, a major consideration is that the stress resulting from the sawing process causes serious peeling near the test pads at the die corners. This results in delamination at the interface between the multiple layers at the die corners. Delamination impacts the reliability of the device and contributes to production of stringers (residual materials) that interfere with further processing and testing of the integrated circuit.
U.S. patent application Ser. No. 10/675,862 discusses a design rule for reducing the peeling of low-k dielectric materials at the corners of dies. Referring to FIG. 1, a top view of a wafer with dies is shown. The semiconductor wafer 1 comprises dies (or chips) 6 separated from each other by first scribe lines 2 and second scribe lines 4. The first scribe lines 2 extend along a first direction and the second scribe lines 4 extend along a second direction. One of the first scribe lines and one of the second scribe lines define an intersection area 8.
A free area 10, which is shaded, is defined. The free area 10 may include the intersection area 8 and regions near the corners of dies. Preferably, no test pads are placed in the free area.
The above-discussed design rule, however, leads to the restriction of test line placement across scribe lines. With the free area excluding the placement of test pads, test lines, in which test pads are formed, may not be able to cross the free area and may have to be placed on either side of the free area. A direct result is that the test lines need to have lengths less than the length of the dies. When the test line length is greater than the available length of dies, extra space may have to be reserved between the dies in order to place the test lines. This results in the waste of wafer area and a reduction in the number of chips per wafer.
What is needed, therefore, is a novel design rule and resulting structure that may reduce the peeling of low-k dielectric material, while at the same time applying the least possible restriction to test line design and placement.